The present invention relates to a method of manufacturing high-density, multi-metal layer semiconductor devices exhibiting reliable interconnection patterns. The invention has particular applicability in manufacturing high-density, multi-metal layer semiconductor devices with design features of 0.25 micron and under.
The escalating requirements for high densification and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.25 micron and under, such as 0.18 micron, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal forming technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon (Si), with conductive contacts formed therein for electrical connection with an active region in or on the substrate, such as a source/drain region. A metal layer, such as of aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask having a pattern corresponding to a desired conductive pattern is formed on the metal layer. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is then planarized, for example, by conventional etching or chemical-mechanical polishing (CMP) techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 micron and below, such as 0.18 micron and below, it becomes increasingly difficult to satisfactorily fill in the interwining spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable inter-level interconnection structure. A through-hole is typically formed in a dielectric layer to expose a selected portion of an underlying metal feature, wherein the exposed portion of the metal feature at the bottom of the through-hole serves as a contact pad. Upon filling the through-hole with conductive material, such as a metal plug, to form a conductive via, the bottom surface of the conductive via is in contact with the underlying metal feature.
Because many large scale integration (LSI) devices presently manufactured are very complex and require multiple levels of metallization for interconnections, it has been common to repeat the above-described via formation process multiple times, e.g., to form as many as five levels of metallization interconnected by conductive vias. A semiconductor device of the above-described type including, for illustrative purposes, three levels of metallization, and a manufacturing process therefor is explained in more detail below with reference to FIG. 1.
As schematically shown in FIG. 1, a semiconductor device 1 of the above-described type comprises a semiconductor substrate 8, typically a doped monocrystalline silicon wafer, having formed therein or thereon at least one active region (not shown for illustrative simplicity), e.g. a source/drain region, a transistor, a diode, and/or other semiconductor elements well known in the art. A first dielectric layer 9 of e.g. a silicon oxide, is formed over substrate 8 and includes at least one electrical contact 10, schematically shown for illustration, for electrically connecting the active structure(s) of semiconductor substrate 8 to a first metal feature 11 comprising a first patterned metal layer formed over first dielectric layer 9. First metal feature 11 is typically formed as a composite structure comprising a thin lower metal layer 11A, of e.g., titanium (Ti) or tungsten (W), a thicker intermediate or primary conductive layer 11B, of e.g., aluminum (Al) or an Al alloy, and an upper, thin, electrically conductive antireflective coating (ARC) 11C, of e.g., titanium nitride (TiN). After formation of the first metal feature 11, a second dielectric layer 12, referred to as a xe2x80x9cgap-fillxe2x80x9d layer, is deposited to fill the interwiring spaces 12A, i.e., the spaces between the first metal features 11. Materials employed for the gap-filling second dielectric layer 12 include, for example, spin-on glass (SOG), high density plasma oxide (HDPO), and low dielectric constant (xe2x80x9clow kxe2x80x9d) materials having an as-deposited dielectric constant below 3.9, such as polytetrafluoroethylene (TEFLON(trademark)), parylene, polyimide, hydrogen silsesquioxane (HSQ), and benzocyclobutene (BCB), the latter two materials being preferred.
A third dielectric layer 13, typically a silicon oxide obtained by plasma enhanced chemical vapor deposition (PECVD) of silane (SiH4) in an N2O atmosphere or by PECVD of tetraethylorthosilicate (TEOS) in the presence of oxygen, is then formed over the second dielectric layer 12 and planarized. A thorough-hole 14, extending through the second and third dielectric layers 12 and 13, is then formed in accordance with conventional practices so that an upper surface portion 11D of the first metal feature 11 is exposed by and encloses the bottom opening of the through-hole 14, thereby providing a contact pad for a metal plug 15, typically of tungsten (W), forming a via 16. Layer 17 shown as lining the internal surfaces of the through-hole 14, is formed prior to metal plug 15 filling and serves as an adhesion promoting and/or barrier layer. Layer 17 is typically formed of an electrically conductive refractory material such as TiN, Tixe2x80x94W, and Tixe2x80x94TiN.
Second metal feature 18 comprising a metal composite similar to first metal feature 11 is then formed by depositing a composite metal layer atop the third dielectric layer 13 and in electrical contact with the first metal feature 11 through via 16, and patterning the layer by means of conventional techniques. Conductive via 16 thus electrically connects first metal feature 11 with second metal feature 18. As illustrated, second metal feature 18 comprises a thin, lower metal layer 18A, thicker intermediate or primary layer 18B, and thin, upper, electrically conductive AR layer 18C.
After formation of the second metal feature 18, a fourth dielectric layer 19 of low k gap-fill material similar to that of second dielectric layer 12 is formed so as to fill the interwiring spaces 19A between the second metal features 18. Fifth dielectric layer 20 of a material similar to that of third dielectric layer 13 is then formed over fourth dielectric layer 19 and planarized by such techniques as employed previously with third dielectric layer 13. As before, a through-hole 21 is formed to extend through fourth and fifth dielectric layers 19, 20 so as to expose a portion 18D of the upper surface of the second metal feature 18 for serving as a contact pad. Metal plug 22 filling through-hole 21 and constituting a second electrically conductive via 23 is formed similarly to first via 16, i.e. by depositing a layer 24 of adhesion promoting and/or barrier material on the internal surface of through-hole 21 prior to filling with metal plug 22.
As illustrated, a third metal feature 25, formed of a composite of layers 25A, 25B, and 25C analogous to layers 11A, 11B, 11C, 18A, 18B, 18C of the first and second metal features 11 and 18, is then formed over fifth dielectric layer 20 and in electrical contact with metal plug 22 of via 23 which electrically connects the second and third metal features 18 and 25.
The above-described process of metal feature formation, dielectric gap-filling, and via formation may be repeated, as desired, in order to fabricate high-density large scale integration (LSI) devices with multiple levels of interconnection. Typical devices currently manufactured include up to five levels of such metallization interconnected by vias.
The impetus for achieving increased component density and attendant reduction in feature size in semiconductor structures such as described above generates numerous problems. For example, as feature sizes, e.g. metal lines and interwiring spaces, shrink to 0.25 micron and below, it becomes increasingly difficult to satisfactorily fill in (i.e. gap fill) the interwiring spacings with a dielectric gap-filling material and obtain adequate step coverage.
In addition, such dielectric gap filling thin films must be capable of serving multiple purposes, including: preventing unwanted shorting of neighboring conductors or conducting levels, by acting as a relatively rigid insulating spacer; preventing corrosion or oxidation of metal conductors, by acting as a barrier to moisture and mobile ions; filling deep, narrow gaps between closely spaced conductors; and planarizing uneven circuit topography so that a level of conductors can then be reliably deposited on a film surface which is substantially flat. Another important requirement of such dielectric thin films is a relatively low dielectric constant k, as compared to silicon dioxide (k=3.9), to lower power consumption, crosstalk, and signal delay for closely spaced conductors.
Dielectric thin films deposited from hydrogen silsesquioxane (HSQ) resins have been found to possess many of the above-recited properties desirable for gap-filling applications. As applied to multi-level semiconductor devices of the type illustrated in FIG. 1, HSQ offers many advantages as a gap-filling dielectric material for use as e.g. the second and fourth dielectric layers 12 and 19, respectively, as well as for sixth, eighth, tenth, etc. dielectric gap filling layer required for metallization levels in excess of those shown in the example of FIG. 1. HSQ is relatively carbon-free, thereby rendering it unnecessary to etch it back below the upper surface of the metal lines 11, 18, and 25 in order to avoid poisoned via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 micron employing conventional spin-on equipment. As deposited, HSQ is considered a relatively low k material (k=2.9-3.0) compared to silicon dioxide grown by a thermal oxidation or chemical vapor deposition (CVD) process (k=3.9-4.2). The mentioned dielectric constants are based upon a scale wherein 1.0 represents the dielectric constant of air. However, HSQ is hydrophilic, i.e. it has a propensity to absorb moisture which can deleteriously affect metal adhesion thereto, increase metal corrosion, and degrade circuit performance.
Other hydrogen-containing low k materials suitable for use as dielectric gap filling layers in metallization processing include, but are not limited to parylene, polyimide, and benzocyclobutene (BCB).
However, in applying HSQ and other such hydrophilic, low k dielectric materials (e.g. BCB) to multilevel metallization processing, it was found that such materials tend to decompose and lose their low k property when subjected to high temperatures, as may be encountered during metallization. For example, and with reference to the device illustrated in FIG. 1, it was found necessary, in order to ensure adequate adhesion of the metal layers to the dielectric layers and to minimize void formation, to subject each of the second (12) and third (13), fourth (19) and fifth (20), etc. dielectric layer pairs to a heat treatment to remove adsorbed water vapor and/or oxygen molecules from the surfaces of the dielectric layers prior to metallization of the first (14), second (21), etc. through-holes and deposition of the first (11), second (18), third (25), etc. metal layers. Such predeposition degassing heat treatments typically comprise heating the semiconductor wafer with the aforementioned dielectric layer pairs formed thereon to temperatures in the range of about 250xc2x0 C. to about 450xc2x0 C. for about 30 seconds to about 200 seconds in a dry, inert atmosphere. In a device having five (5) metallization levels, the dielectric layer pair at the first metallization level (M1) will experience four (4) such degas heat treatments, the dielectric pair at the second metallization level (M2) will experience three (3) degas heat treatments, etc. Thus the dielectric layer pairs, particularly those of the lower metallization levels, experience cumulative degassing treatments at elevated temperatures which result in degradation of at least the HSQ layer of the dielectric layer pairs with consequential poor adhesion and void formation of the metallization layers.
Thus, there exists a need for a degassing heat treatment which substantially reduces or eliminates degradation of dielectric layer pairs during metallization processing.
An advantage of the present invention is a method of manufacturing a high density, multi-metal layer semiconductor device with an improved metallization structure.
Another advantage of the present invention is a method for reducing or substantially eliminating degradation of low k dielectric gap filling layers in multi-metal level semiconductor devices.
Still another advantage of the present invention is a method for minimizing the time during which a multi-metal level semiconductor device is subjected to high temperature degassing of dielectric layers prior to metal deposition thereon.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a multilevel semiconductor device, which method comprises:
forming a first dielectric layer on a substrate;
forming a first patterned metal layer on the first dielectric layer, the first patterned metal layer having gaps therein and comprising a first metal feature;
forming a second dielectric layer covering the first patterned metal layer and filling the gaps, the second dielectric layer comprising a low dielectric constant (low k) material;
forming a third dielectric layer over the second dielectric layer;
forming a first through-hole in the second and third dielectric layers, the first through-hole exposing a portion of the upper surface of the first metal feature;
subjecting the exposed surfaces of the second and third dielectric layers to a degassing heat treatment at a temperature below which the low k material is degraded and for a first time interval;
immediately after the degassing heat treatment, depositing, for a second time interval, a plug of electrically conductive material filling the first through-hole, thereby defining a first via; and
depositing, for a third time interval, a first electrically conductive layer on the third dielectric layer and in electrical contact with the first via;
wherein, the first time interval is equal to or shorter than the longer of the second and third time intervals.
According to a further embodiment, the method of the present invention comprises the further steps of:
patterning the first electrically conductive layer to form a second patterned metal layer having gaps therein and defining a second metal feature electrically connected to the first metal feature through the first via;
forming a fourth dielectric layer covering the second patterned metal layer and filling the gaps therein, the fourth dielectric material comprising a low k material;
forming a fifth dielectric layer over the fourth dielectric layer;
forming a second through-hole in the fourth and fifth dielectric layers, the second through-hole exposing a portion of the upper surface of the second metal feature;
subjecting the exposed surfaces of the fourth and fifth dielectric layers to a degassing heat treatment at a temperature below that which the low k material(s) of the second and fourth dielectric layers is (are) degraded and for a fourth time interval;
immediately after the preceding heat treatment, depositing, for a fifth time interval, a plug of electrically conductive material filling the second through-hole, thereby defining a second via; and
depositing, for a sixth time interval, a second electrically conductive layer on the fifth dielectric layer and in electrical contact with the second via;
wherein, the fourth time interval is equal to or less than the longer of the fifth and sixth time intervals.
In preferred embodiments according of the present invention, the low k dielectric material is HSQ and each of the degassing heat treatments is performed at a temperature less than about 400xc2x0 C. for less than about 45-60 seconds. In other preferred embodiments, the low k dielectric material is BCB and each of the degassing heat treatments is performed at a temperature less than about 350xc2x0 C. for less than about 45-60 seconds.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.